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Parag K. Lala's Publications

Books (selected)

Self-Checking and Fault-Tolerant Digital Design  (345 citations in Google Scholar), Morgan-Kaufmann  (2001)

Principles of Modern Digital Design , John Wiley and Sons (2007)

An Introduction to Logic Circuit Testing, Morgan-Claypool  (2008)

International Journal and Conference Publications (selected)

 “Self-Checking Logic for FPGAs”, P.K. Lala and A. Burress, IEEE Trans. on Instrumentation and Measurement (special issue on Testability), October, 2003

“ On self-healing digital system design”,  P.K. Lala, B. Kiran Kumar and J.P. Parkerson, Microelectronics Journal: Circuits and Systems, Volume 37, Issue 4 , April 2006.  

“A Single Error Correcting and Double Error Detecting Coding Scheme”, P.K. Lala, P. Thenappan,  and M.T. Anwar”, IEE Electronics Letters, May 6, 2005.

“Reversible logic design with online testability”, D.P. Vasudevan, P.K. Lala, J. Di and .P. Parkerson, IEEE Trans. Instrumentation and Measurement (special section on VLSI Test), vol.55, April 2006.

“Cellular array-based delay-insensitive asynchronous circuit design for nanocomputing system design”,  J. Di and P.K. Lala”, , Jour. Electronic Testing: Theory and Applications, 23,  June 2007   

“Self-checking carry-select adder design based on two-rail encoding”, D.P. Vasudevan, P.K. Lala  and J.P. Parkerson”, IEEE Trans. Circuits and Systems I: Regular papers, vol.54,  December 2007.

“An approach for designing on-line testable sequential circuits at the transistor level”,   P.K. Lala,  A. Mathews  and  J.P. Parkerson , International Jour. VLSI Design, Hindawi Publication,  May 2010

“A digital hardware- based approach for molecular sequence comparison”, P.K. Lala ,  Journal of Information Engineering, vol.2, issue 3, Sept.2013

 “An efficient key distribution protocol based on BB84”, P. K. Lala,  American Journal of Computing Research Repository.  2(2), 2014

“On-line error detection in a carry-free adder”,  W. Townsend, J.A. Abraham, and P.K. Lala, IEEE International Symp.  On-Line Testing 2003, Rhodes, Greece.   

“On-line detection of faults in carry-select adders”, B. Kiran Kumar and P.K. Lala,  Proc.ACM-IEEE International Test Conference, 2003, Charlotte, NC.

“Fault injection for verifying testability at the VHDL level”, S.R. Seward and P.K. Lala,  Proc. ACM-IEEE International Test Conference, 2003, Charlotte, NC.

“A new reversible logic gate and its applications”, D.P. Vasudevan and P.K. Lala , Proc. International Conf. on VLSI, Las Vegas, 2004.

“A novel approach for on-line testable reversible logic circuit design” , D.P. Vasudevan, P.K. Lala and J.P. Parkerson, IEEE 2004 IEEE Asian Test Symp.(ATS’04), Taiwan.

“Online testable reversible logic circuit design using NAND blocks”, D.P. Vasudevan, P.K. Lala and  J.P. Parkerson,  Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems  Cannes, France, October 2004.

“On the effect of stuck-at faults on delay-insensitive nanoscale circuits “, J. Di, P.K. Lala, and        

D. Vasudevan, Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems , Monterrey, CA, October 2005

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